1. Technical Field
This invention relates to data extraction filtering devices, and, more particularly, to a digital integrate and dump circuit with a digital output for recovering digital information from an analog input signal.
2. Discussion
There is a desirability for a more efficient recovery of information from an analog signal which is often corrupted with noise. Generally, an ideal form of a matched filter known as an integrate and dump filter provides optimum recovery of information with maximum processing gain and low bit error rate over each baud interval. Typical integrate and dump filters include filtering devices for integrating a voltage input over a specified time interval, and thereafter, providing the result of the integration as the filter output. Such a device is generally employed for determining the cumulative polarity of the input signal over the integration time interval.
Generally, prior art integrate and dump filters do not achieve the highest efficiency with maximum processing gain and lowest bit error rate possible. This is especially true for high data rates. A typical circuit provides alternating integrate and dump circuits which require separate integrate and dump functions. The separate integrate and dump circuits essentially alternate in function from bit interval to bit interval. This results in an inefficiency created by the separate dump interval which is not allowed to happen instantaneously as desired. This is due to the separate dump interval requiring a large portion of the baud interval thereby leaving a shorter interval for the integration function. As a result, less energy is allowed to be accounted for during the integration process. In addition, the separate dump interval usually requires excess circuitry, resulting in a more expensive and bulky circuit configuration.
Additionally, the dumping process is not always accurate due to the fact that some charge is left on the integrator's capacitor. This charge is an error that is dependent on the value of the previous baud and, therefore, is undesirable.
It is therefore desirable to obtain a more efficient integrate and dump circuit that does not suffer from the inefficiency of a separate dump interval. Furthermore, it is desirable to have a high efficiency integrate and dump circuit that provides maximum processing gain and lowest bit error rate possible.